Phase-lock loop with independent phase and frequency adjustments

ABSTRACT

A PLL is provided with separate phase and frequency adjustment circuits to adjust the frequency of a produced internal clock independently from adjusting its phase. The phase adjustment circuit determines a phase error between the internal clock and an external clock, and averages the phase error over a predetermined time period to produce the corresponding control current. The frequency adjustment circuit detects the difference between the frequency of the internal clock and the frequency of the external clock to determine a frequency error. An accumulator accumulates the frequency error during the predetermined time period to produce the corresponding control current. Based on values of the control currents produced by the phase and frequency adjustment circuits, a current calculator calculates a resulting value of the control current to be applied to a CCO to modify its frequency so as reduce the frequency and phase differences.

TECHNICAL FIELD

[0001] The present invention relates to a phase-lock loop (PLL), andmore particularly, to a PLL with independent phase and frequencyadjustment circuits that may be used in synchronous memory devices.

BACKGROUND ART

[0002] An external signal supplied to an electrical system is inevitablycorrupted by additive noise. For various applications, such as clockgeneration, a highly stable signal is required. Therefore, the externalsignal should be processed to remove as much noise as possible.

[0003] To produce a stable internal signal based on the external signal,a conventional PLL may employ a current-controlled oscillator (CCO),whose frequency is controlled by a control current. A phase detectorcompares the phase of the external signal against the phase of the CCOoutput to determine an error signal that indicates the phase difference.To suppress noise, the error signal is averaged over some length oftime, and the average value is used to produce the control currentapplied to the CCO to change its frequency in a direction that reducesthe phase difference between the input signal and the CCO output.

[0004] Referring to FIG. 1, a conventional PLL 30 for producing a highlyaccurate internal clock INT.CLK based on an external reference clockEXT.CLK may comprise a phase detector 32 supplied with the EXT.CLKsignal. Via a charge pump 34, a loop filter 36, and a voltage-to-currenttransformer 38, the output of the phase detector 32 is coupled to acontrol input of a CCO 40. A level shifting and buffering circuit 42coupled to the CCO output produces the INT.CLK signal supplied via afeedback loop to the phase detector 32.

[0005] The phase detector 32 compares the phase Φint of the INT.CLKsignal with the phase next of the EXT.CLK signal to generate a phaseerror voltage Vd=Kc(Φext−Φint), where Kc is called the phase detectorgain factor and is measured in units of volts per radian. The gainfactor Kc is determined by the charge pump 34 used to charge anddischarge the loop filter 36.

[0006] The phase error voltage Vd is filtered by the loop filter 36 thatsuppresses noise and high-frequency components of the phase errorsignal. The voltage-to-current transformer 38 converts the filteredphase error voltage into control current that defines the frequency ofthe CCO 40. The level shifting and buffering circuit 42 translates thelevel of the CCO output into a level required for a system supplied withthe INT.CLK signal, and provides an interface between the PLL and thissystem.

[0007] When the loop is locked, the control current is such that thefrequency of the CCO is equal to the average frequency of the EXT.CLKsignal. For each cycle of the EXT.CLK signal there is one, and only one,cycle of the CCO output. To maintain the control current needed forlock, it is generally necessary to have a nonzero output from the phasedetector. Consequently, the loop operates with some phase error present.

[0008] Since frequency is the derivative of phase, a conventional PLLperforms frequency adjustment of an incoming signal simultaneously withadjustment of its phase. The frequency and phase adjustments are carriedout using the phase detector 32 which performs phase comparison at thefrequency of the CCO output signal supplied via the feedback loop. Theerror signal at the output of the phase detector 32 indicatesinstantaneous phase difference. The loop filter 36 provides averaging ofthe error signal over some time interval to establish an average valueused for producing the control current applied to the CCO 40. Deviationof the CCO from its center frequency caused by the control current maybe described as dΦ₀/dt, where Φ₀ is the phase of the CCO output equal tothe phase Φint of the INT.CLK signal produced by the PLL 30. In otherwords, a conventional PLL performs frequency and phase adjustments inthe same loop.

[0009] A PLL starts out in an unlocked condition and must be broughtinto lock. The process of bringing a conventional PLL into lock is oftena slow and unreliable process performed by the phase detector 32 thattracks variations of the INT.CLK signal with respect to the referenceEXT.CLK signal. In particular, when the INT.CLK signal leads in phasewith respect to the EXT.CLK signal, or the frequency of the INT.CLKsignal is higher than the frequency of the EXT.CLK signal, the phasedetector 32 causes the charge pump 34 to increase the potential at theoutput of the loop filter 36. In response, the voltage-to-currenttransformer 38 reduces the value of the control current applied to theCCO 40. As a result, the frequency of the INT.CLK signal at the outputof the CCO 40 reduces. The reduction of the INT.CLK frequency causes thedelay of the INT.CLK signal to reduce its phase lead with respect to theEXT.CLK signal.

[0010] By contrast, when the INT.CLK signal lags in phase with respectto the EXT.CLK signal, or the frequency of the INT.CLK signal is lowerthan the frequency of the EXT.CLK signal, the phase detector 32 causesthe charge pump 34 to reduce the potential at the output of the loopfilter 36. In response, the voltage-to-current transformer 38 increasesthe value of the control current applied to the CCO 40. When the controlcurrent increases, the frequency of the INT.CLK signal at the output ofthe CCO 40 increases. The INT.CLK frequency increase causes the INT.CLKsignal to reduce its phase lag with respect to the EXT.CLK signal.

[0011] However, in conventional PLLs, it takes a long time to reach alocked state when the frequency of the INT.CLK signal becomes close tothe frequency of the EXT.CLK signal. It would be desirable to provide aPLL that reduces the time required to bring the loop into a lockedstate.

[0012] If the INT.CLK frequency is dose enough to the EXT.CLK frequency,a conventional PLL locks up with just a phase transient. There is nocycle slipping prior to lock. It would be desirable to provide a PLLthat operates in a wide frequency range over which the loop could bebrought into a locked state without slipping cycles.

[0013] A small phase error enables a PLL to maintain a locked state.However, if the error becomes so large that the CCO skips cycles, thePLL is considered to have lost lock. A recovery time is required toacquire lock again. It would be desirable to provide a PLL that requiresa short recovery time.

DISCLOSURE OF THE INVENTION

[0014] Accordingly, one advantage of the present invention is inproviding a PLL that reduces the time required to bring its loop into alocked state, compared to a conventional PLL.

[0015] Another advantage of the present invention is in providing a PLLthat operates in a wide frequency range over which its loop can bebrought into a locked state without slipping cycles.

[0016] A further advantage of the present invention is in providing aPLL that requires a short recovery time.

[0017] The above and other advantages of the invention are achieved, atleast, in part, by providing a system for generating an internal clocksignal in response to an external clock signal. The system comprises aphase adjustment circuit responsive to the external clock signal and theinternal clock signal for producing a phase adjustment signal thatrepresents difference between the phase of the external clock signal andthe phase of the internal clock signal. A frequency adjustment circuitis responsive to the external clock signal and the internal clock signalfor producing a frequency adjustment signal that represents differencebetween the frequency of the external clock signal and the frequency ofthe internal clock signal. A control value calculator is responsive tothe phase adjustment signal and the frequency adjustment signal forproducing a resulting control signal supplied to a signal-controlledoscillator that generates the internal clock signal at an internal clockfrequency deviating in response to the resulting control signal.

[0018] In accordance with a first embodiment of the present invention,the frequency adjustment circuit may comprise a frequency detectorresponsive to the external and internal clock signals for producing aninstantaneous value of a frequency error signal that indicatesdifference between instantaneous frequencies of the internal clocksignal and the external clock signal. An accumulator may be coupled tothe frequency detector for accumulating instantaneous values of thefrequency error signal over a preset time period to produce anaccumulated signal that indicates an average value of the frequencydifference for the preset time period. An adjusting circuit may becoupled to the accumulator for adjusting the accumulated signal toproduce the frequency adjustment signal.

[0019] In accordance with another embodiment of the present invention,the frequency adjustment circuit may comprise a first counter responsiveto the external clock signal and the internal clock signal for countingthe number of periods of the external clock signal in a half cycle ofthe internal clock signal in which the internal clock signal is at afirst logic level. A second counter may count the number of periods ofthe external clock signal in a half cycle of the internal clock signalin which the internal clock signal is at a second logic level. A thirdcounter may count the number of periods of the internal clock signal ina half cycle of the external clock signal in which the external clocksignal is at the first logic level. Finally, a fourth counter may countthe number of periods of the internal clock signal in a half cycle ofthe external clock signal in which the external clock signal is at thesecond logic level.

[0020] First, second, third and fourth adders may be respectivelycoupled to the first, second, third and fourth counters for accumulatingn-bit counts produced by the first, second, third and fourth counters togenerate m-bit accumulated values. First, second, third and fourthdecoders may be respectively coupled to the first, second, third andfourth adders to generate first, second, third and fourth frequencycontrol values supplied, together with a base value representing thephase adjustment signal, to the control value calculator. In response,the control value calculator may add the first or second frequencycontrol values to the base value, or subtract the third or fourthfrequency control values from the base value.

[0021] A reference current generator may be provided for supplying thefirst, second, third and fourth decoders with reference current topresent the first, second, third and fourth frequency control values asfirst, second, third and fourth frequency control currents. The basevalue may be represented by base current. In response to the first,second, third and fourth frequency control currents and the basecurrent, the control value calculator may produce the resulting controlcurrent supplied to the signal-control oscillator to adjust frequencyand phase of the internal clock signal.

[0022] In accordance with a further embodiment of the present invention,the frequency adjustment circuit may comprise a first frequency dividersupplied with the internal clock signal for producing a divided internalclock signal at a frequency equal to the frequency of the internal clocksignal divided by a preset number. A second frequency divider may besupplied with the external clock signal for producing a divided externalclock signal at a frequency equal to the frequency of the external clocksignal divided by the preset number.

[0023] A first counter may be coupled to the first frequency divider andsupplied with the external clock signal for counting the number ofperiods of the external clock signal in a half cycle of the dividedinternal clock signal. A second counter may be coupled to the secondfrequency divider and supplied with the internal clock signal forcounting the number of periods of the internal clock signal in a halfcycle of the divided external clock signal.

[0024] First and second adders may be respectively coupled to the firstand second counters for accumulating n-bit counts produced by the firstand second counters to generate m-bit accumulated values. First andsecond decoders may be respectively coupled to the first and secondadders to generate first and second frequency control values supplied tothe control value calculator. In response, the control value calculatormay add the first frequency control value to the base value, or subtractthe second frequency control value from the base value.

[0025] In accordance with another embodiment of the present invention, afine adjustment circuit may be provided for fine frequency tuning of thesignal-controlled oscillator, in addition to rough frequency adjustmentcarried out by the frequency adjustment circuit, and phase adjustmentprovided by the phase adjustment circuit. The fine adjustment circuitmay comprise a delay monitor for delaying the external clock signal by adelay amount defined by a period of the signal-controlled oscillator. Acomparator may compare a delayed external clock signal produced by thedelay monitor with the external clock signal to generate a fine controlsignal supplied to the control value calculator to modify the resultingcontrol signal.

[0026] In accordance with a further embodiment of the present invention,the fine adjustment circuit may comprise a delay model responsive to theexternal clock signal for producing a first output signal delayed by afirst delay time smaller than a period of the signal-controlledoscillator, and for producing a second output signal delayed by a seconddelay time larger than the period of the signal-controlled oscillator.

[0027] A logic circuit may be coupled to the delay model and suppliedwith an input signal to the delay model for determining logic levels ofthe first and second output signals when the input signal goes from afirst level to a second level. The logic circuit may produce a downsignal when both the first and second output signals are at the firstlevel. An up signal may be produced when both the first and secondoutput signals are at the second level when said input signal goes fromthe first level to the second level. The control value calculator mayincrease a value of the resulting control signal in response to the upsignal, or decrease the value of the resulting control signal inresponse to the down signal.

[0028] A frequency divider may be coupled to the delay model forproducing its input signal at a frequency equal to the frequency of theexternal clock signal divided by a predetermined amount.

[0029] A first adder may be coupled to the logic circuit foraccumulating instantaneous values of the up signal to generate an m-bitaccumulated value of the up signal. A second adder may be coupled to thelogic circuit for accumulating instantaneous values of the down signalto generate an mbit accumulated value of the down signal. First andsecond decoders may be respectively coupled to the first and secondadders to generate first and second fine tuning values supplied to thecontrol value calculator. In response, the control value calculator mayadd the first fine tuning value to the base value, or subtract thesecond fine tuning values from the base value.

[0030] The signal-controlled oscillator may comprise a ring oscillatorhaving k serially connected inverter stages, where k is an odd number.The delay model may comprise more than 2k serially connected delaystages similar to the inverter stages in the ring oscillator. The firstoutput signal may be produced at an output of delay stage 2k−l, where lis an integer. For example, l may equal to 1. The second output signalmay be produced at an output of delay stage 2k+l.

[0031] Also, the fine adjustment circuit may comprise a referencecurrent generator for supplying the first and second decoders withreference current to present the first and second fine tuning values asfirst and second fine tuning currents. The control value calculator mayproduce resulting control current supplied to the ring oscillator totune its frequency.

[0032] In accordance with a method of the present invention, to producean internal clock signal in synchronism with an external clock signal,the following steps are carried out:

[0033] comparing phase of the internal clock signal with phase of theexternal clock signal to produce a phase adjustment signal representingdifferences in phase and frequency between the internal clock signal andthe external clock signal,

[0034] comparing frequency of the internal clock signal with frequencyof the external clock signal independently from the step of phasecomparing, to produce a frequency adjustment signal representingdifference between the frequency of the internal clock signal and thefrequency of the external clock signal,

[0035] producing a control signal representing the phase adjustmentsignal and the frequency adjustment signal, and

[0036] controlling a signal-controlled oscillator by the control signalto produce the internal control signal synchronized with the externalcontrol signal.

[0037] The steps of phase comparing and frequency comparing may becarried out by separate circuits.

[0038] Further, fine tuning of the signal-controlled oscillator may becarried out when the frequency of the internal clock signal is close tothe frequency of the external clock signal. The step of fine tuning maycomprise the step of delaying the external clock signal by a delay timedefined by a period of the signal-controlled oscillator. A delayedexternal clock signal may be compared with the external clock signal toproduce a fine tuning signal. The resulting control signal may beproduced so as to represent the phase adjustment signal, the frequencyadjustment signal and the fine tuning signal.

[0039] In accordance with another aspect of the present invention, amemory device supplied with -an external clock signal comprises:

[0040] a memory cell array for storing data, and an internal synchronousclock signal generator responsive to the external clock signal forproducing an internal clock signal supplied to internal circuits of thememory device to control various data reading and writing operations.

[0041] The internal synchronous clock signal generator includes:

[0042] a phase adjustment circuit responsive to the external clocksignal and the internal clock signal for producing a phase adjustmentsignal representing difference between phase of the external clocksignal and phase of the internal clock signal,

[0043] a frequency adjustment circuit responsive to the external clocksignal and the internal clock signal for producing a frequencyadjustment signal representing difference between frequency of theexternal clock signal and frequency of the internal clock signal,

[0044] a control value calculator responsive to the phase adjustmentsignal and the frequency adjustment signal for producing a resultingcontrol signal, and

[0045] a signal-controlled oscillator responsive to the resultingcontrol signal for supplying the internal circuits with the internalclock signal modified in response to the resulting control signal.

[0046] Still other advantages of the present invention will becomereadily apparent to those skilled in this art from the followingdetailed description, wherein only the preferred embodiment of theinvention is shown and described, simply by way of illustration of thebest mode contemplated of carrying out the invention. As will berealized, the invention is capable of other and different embodiments,and its several details are capable of modifications in various obviousrespects, all without departing from the invention. Accordingly, thedrawing and description are to be regarded as illustrative in nature,and not as restrictive.

BRIEF DESCRIPTION OF DRAWINGS

[0047]FIG. 1 illustrates a conventional PLL.

[0048]FIG. 2 shows a schematic block diagram of an exemplary system inwhich a PLL of the present invention may be employed.

[0049]FIG. 3 illustrates independent phase and frequency adjustments inthe PLL of the present invention.

[0050]FIG. 4 is a simplified block diagram of the PLL having a phaseadjustment circuit and a frequency adjustment circuit.

[0051]FIG. 5 illustrates an embodiment of the present invention having aplurality of counters in the frequency adjustment circuit.

[0052]FIGS. 6 and 7 show waveforms illustrating operations of thefrequency adjustment circuit in FIG. 5.

[0053]FIG. 8 illustrates another embodiment of the present inventionemploying frequency dividers and counters in the frequency adjustmentcircuit.

[0054]FIGS. 9 and 10 show waveforms illustrating operations of thefrequency adjustment circuit in FIG. 8.

[0055]FIG. 11 is a simplified block diagram illustrating a furtherembodiment of the present invention employing a fine adjustment circuit,in addition to the phase and frequency adjustment circuits.

[0056]FIG. 12 is a block diagram presenting the fine adjustment circuitand the frequency adjustment circuit in more detail.

[0057]FIG. 13 illustrates an example of a CCO.

[0058]FIG. 14 shows a delay model employed in the fine adjustmentcircuit.

[0059] FIGS. 15-17 are waveforms illustrating operations of the fineadjustment circuit in FIG. 12.

[0060]FIG. 18 illustrates supplying command clocks to control the PLLoperations.

[0061]FIG. 19 illustrates an example of the state transition of the PLLshown in FIG. 18.

BEST MODE FOR CARRYING OUT THE INVENTION

[0062] Reference is now made to FIG. 2 that shows a schematic blockdiagram of an exemplary system in which the present invention may beadvantageously employed. The exemplary system is a synchronoussemiconductor memory device 100, such as synchronous dynamicrandom-access memory (SDRAM), synchronized by clock signals to reducethe memory access time. The memory device 100 may comprise a clockbuffer 102 supplied with an external clock signal EXT.CLK. Via the clockbuffer 102, the EXT.CLK signal is sent to an internal synchronous signalgenerator 104 which contains a PLL for producing an internal clocksignal INT.CLK. An internal control signal generator 106 uses theINT.CLK signal received from the internal synchronous signal generator104 to generate internal control signals for controlling various memoryoperations.

[0063] The synchronous memory device 100 contains a memory cell array108 having memory cells arranged in rows and columns. An address buffer110 supplied with the INT.CLK signal receives external address signalsto produce an internal row address signal and an internal column addresssignal.

[0064] A row decoder 112 is controlled by the internal control signalfrom the internal control signal generator 106 to decode the internalrow address signal and select a corresponding row in the memory cellarray 108. A column decoder 114 is controlled by the internal controlsignal from the internal control signal generator 106 to decode theinternal column address signal that enables the column decoder 114 tosimultaneously select a plurality of columns in the memory cell array108 and sense amplifiers 116 connected to the selected columns to readand amplify data stored in the memory cells coupled to the selected row.

[0065] The sense amplifiers 116 controlled by the internal controlsignal from the internal control signal generator 106 connects theselected columns to an internal data bus in response to a column selectsignal from the column decoder 114. A selector circuit 118 controlled bythe internal control signal from the internal control signal generator106 selects data corresponding to an internal select address signalsupplied from the address buffer 110. An output circuit 120 iscontrolled by the internal control signal generator 106 to supply theselected data to a data input/output terminal 122.

[0066] External command signals are supplied via a command buffer 124 toa command decoder 126 which decodes the external commands to generatecommand clocks A-E for controlling the clock buffer 102 and variouselements of the PLL in the internal synchronous signal generator 104 toproduce the INT.CLK signal, as disclosed in more detail later.

[0067] Accordingly, operations of the synchronous memory device 100 aresynchronized using the internal clock signal INT.CLK produced by the PLLin the internal synchronous signal generator 104 in response to theexternal clock signal EXT.CLK.

[0068] Referring to FIG. 3, a PLL 140 of the present invention employstwo separate circuits to adjust the frequency of the internal clockINT.CLK independently from adjusting the phase of the internal clock. Ina phase adjustment circuit 142, the PLL 140 detects the phase differenceand frequency difference between the internal clock INT.CLK and theexternal clock EXT.CLK to determine a phase error (step 144). Instacking step 146, the phase error is averaged over a predetermined timeperiod, and its average value may be used to produce the control currentthat reflects the detected phase difference and frequency difference.

[0069] In a frequency adjustment circuit 148, the PLL 140 detects thedifference between the frequency of the INT.CLK signal and the frequencyof the EXT.CLK signal to determine a frequency error (step 150). Then,stacking step 152 is carried out to average the frequency error over thepredetermined time period. The produced average value may indicate thecontrol current corresponding to the detected frequency difference.

[0070] In step 154, the values produced in steps 146 and are used tocalculate a value of the resulting control current to be applied to aCCO to modify its frequency so as to reduce the frequency differencedetected in step 150, and the phase and frequency differences detectedin step 144. The calculation of the resulting control current is carriedout in accordance with the preset algorithm. In step 156, the CCOfrequency deviates in response to the calculated value of the controlcurrent so as to reduce the frequency difference between the internaland external clocks.

[0071] When the external reference clock EXT.CLK is first applied, thefrequency difference between the external and internal clocks may be solarge that the PLL 140 is out of lock. In this case, the frequencyadjustment circuit 148 operates in a mode of rough adjustment to bringthe CCO frequency closer to the frequency of the external clock. Theoperation in the rough adjustment mode is carried out until the locklimit is reached, i.e. until the INT.CLK frequency is close enough tothe EXT.CLK frequency to bring the loop into lock. The phase adjustmentcircuit 142 has little effect when the system 140 is out of lock. TheCCO is controlled almost exclusively by the frequency adjustment circuit148.

[0072] When the frequency adjustment circuit 148 brings the frequencyerror within the lock limit, the locking system 140 goes to a lockedmode of operation to perform accurate phase and frequency adjustment. Inthis mode, the phase adjustment circuit 142 dominates over the frequencyadjustment circuit 148 because of the phase-integrating property of theCCO.

[0073] Referring to FIG. 4, the phase adjustment circuit 142 of the PLL140 may comprise a phase detector 160 having a first input supplied withthe external reference clock EXT.CLK. The internal clock INT.CLK is fedto a second input of the phase detector via a feedback loop. The phasedetector compares the phase of the INT.CLK signal with the phase of theEXT.CLK signal. Since frequency is the derivative of phase, the phasedetector simultaneously compares the frequency of the INT.CLK signalwith the frequency of the EXT.CLK signal. The output of the phasedetector 160 produces a phase error signal indicating instantaneousphase and frequency difference between the INT.CLK signal and theEXT.CLK signal.

[0074] A charge pump 162 is coupled to the output of the phase detector160 for charging or discharging a loop filter 164 connected to thecharge pump 162. The loop filter 164 filters the phase error signal tosuppress noise and eliminate high-frequency components by averaging thevalue of this signal for a predetermined period of time. In other words,the input to the loop filter 164 is a noisy signal, whereas the outputis a cleaned-up version of the phase error signal.

[0075] Two important characteristics of the loop filter 164 are that itsbandwidth is narrow enough to reject large amounts of noise, and thatthe loop filter 164 automatically tracks the error signal frequency whenthe loop is locked. A voltage-to-current transformer 166 may be coupledto the output of the loop filter 166 to convert its voltage into a basecurrent that corresponds to the phase and frequency difference betweenthe INT.CLK and EXT.CLK signals.

[0076] When the INT.CLK signal leads in phase with respect to theEXT.CLK signal, or the frequency of the INT.CLK signal is higher thanthe frequency of the EXT.CLK signal, the phase detector 160 causes thecharge pump 162 to increase the potential at the output of the loopfilter 164. In response, the voltage-to-current transformer 166 reducesthe value of the base current.

[0077] By contrast, when the INT.CLK signal lags in phase with respectto the EXT.CLK signal, or the frequency of the INT.CLK signal is lowerthan the frequency of the EXT.CLK signal, the phase detector 160 causesthe charge pump 162 to reduce the potential at the output of the loopfilter 164. In response, the voltage-to-current transformer 166increases the value of the base current.

[0078] The frequency adjustment circuit 148 of the PLL 140 may contain afrequency detector 168, an accumulator 170 and a current adjuster 172.The frequency detector 168 has its first input supplied with theexternal reference clock EXT.CLK, and its second input provided with theinternal clock INT.CLK via a feedback loop. The output of the frequencydetector 168 produces an instantaneous value of a frequency error signalindicating difference between the instantaneous frequencies of theINT.CLK signal and the EXT.CLK signal.

[0079] The accumulator 170 accumulates instantaneous values of thefrequency error signal over a preset time period to produce an outputcurrent indicating an average value of the frequency difference for thepreset time period. The current adjuster 172 adjusts the currentsupplied from the accumulator 170 to produce a control currentrepresenting the frequency error.

[0080] A current calculator 174 adds or subtracts the control currentvalue produced by the current adjuster 172 to or from the base currentvalue produced by the voltage-to-current transformer 166, depending onwhether the frequency difference between the EXT.CLK and INT.CLK signalsis considered to be a positive or negative value.A CCO 176 has itscontrol input connected to the output of the current calculator 174. Forexample, a ring oscillator having an odd number of inverter stages maybe used as the CCO 176.

[0081] When the external reference clock EXT.CLK is first applied, thefrequency of the CCO 176 may be determined by the base current producedby the voltage-to-current transformer 166 in the phase adjustmentcircuit 142. If the PLL 140 is out of lock, the frequency adjustmentcircuit 148 operates in a mode of rough adjustment to bring the CCOfrequency closer to the frequency of the external clock EXT.CLK. Therough adjustment mode of operation is carried out until the lock limitis reached. The phase adjustment circuit 142 has little effect when thesystem 140 is out of lock. The deviation of the CCO frequency isdetermined almost exclusively by the control current produced by thecurrent adjuster 174 in the frequency adjustment circuit 148. Theresulting current produced by the current calculator 174 is applied tothe control input of the CCO 176. When the value of the resultingcurrent decreases, the frequency at the output of the CCO 176 reduces.When the value of the resulting current increases, the CCO frequencyincreases.

[0082] When the frequency adjustment circuit 148 makes the differencebetween the CCO frequency and the EXT.CLK frequency small enough tobring the frequency error within the lock limit, the PLL 140 goes to alocked mode of operation to perform accurate phase and frequencyadjustment. In this mode, the base current produced in the phaseadjustment circuit 142 dominates over the control current produced inthe frequency adjustment circuit 148 because of the phase-integratingproperty of the CCO 176.

[0083] A level shifting and buffering circuit 178 coupled to the outputof the CCO 176 produces the INT.CLK signal supplied via a feedback loopto the phase detector 160 and the frequency detector 168. The levelshifting and buffering circuit 178 translates the level of the CCOoutput into a level required for a system supplied with the INT.CLKsignal, and interfaces the PLL 140 with this system.

[0084] Due to employing the frequency adjustment circuit 148 in additionto the phase adjustment circuit 142, frequency adjustment is carried outindependently of phase adjustment. This allows the PLL 140 of thepresent invention to reach a locked state substantially faster than aconventional PLL. As a result, the present invention allowssubstantially to reduce a transitional time period from the instant, inwhich the EXT.CLK signal is first applied to the instant, in which theINT.CLK signal becomes synchronized with the EXT.CLK signal.

[0085] Also, the frequency adjustment circuit 148 reduces the recoverytime required for the PLL 140 to reinstate a locked state after goingout of lock, compared to a conventional PLL.

[0086] Moreover, the detection of the EXT.CLK and INT.CLK frequencydifference using the frequency detector 168 enables the PLL 140 tosubstantially increase a frequency range, within which lock-inoperations may be performed, compared to a conventional PLL.

[0087]FIG. 5 illustrates an exemplary embodiment of the PLL that employsa frequency adjustment circuit 180 in addition to a phase adjustmentcircuit 182. The frequency adjustment circuit 180 may comprise fourcounters A, B, C and D labelled by reference number 184. Each of thecounters 184 is supplied with an external reference clock EXT.CLK, andan internal clock INT.CLK, or with a reference clock EXT.CLK/ invertedwith respect to the EXT.CLK signal, and an internal clock INT.CLK/inverted with respect to the INT.CLK signal. As discussed above, theINT.CLK signal is provided from the output of the PLL via a feedbackloop.

[0088] The counters 184 count the number of clocks in the EXT.CLK andINT.CLK signals, and produce n-bit counts representing the result oftheir counting operations. For example, the counter A may be used forcounting the number of EXT.CLK periods in a high-level half cycle of theINT.CLK signal. The counter B may count the number of EXT.CLK periods ina lowlevel half cycle of the INT.CLK signal. The counter C may count thenumber of INT.CLK periods in a high-level half cycle of the EXT.CLKsignal. Finally, the counter D may me used for counting the number ofINT.CLK periods in a low-level half cycle of the EXT.CLK signal. In thiscase, counters B and D are supplied with the EXT.CLK/ and INT.CLK/signals produced by inverters I coupled to the inputs of the counters Band D.

[0089] An adder 186 is coupled to the output of each counter 184 foraccumulating the n-bit counts produced by the corresponding counter 184to generate an m-bit value. A current decoder 188 is coupled to theoutput of each adder 186 for producing the control current thatrepresents the output value of the corresponding adder 186.

[0090] A current generator 190 provides each of the current decoders 180with a reference value of current. The current decoders 180 modify thereference current in accordance with the output values of thecorresponding adders 186 to produce the control current.

[0091] The phase adjustment circuit 182 may comprise a phase detector192 supplied with the EXT.CLK signal and the INT.CLK signal to produce aphase error signal representing phase and frequency differences betweenthe EXT.CLK signal and the INT.CLK signal. The phase error signal isprocessed by a charge pump 194, a loop filter 196 and avoltage-to-current transformer 198 to produce a base currentcorresponding to the phase error signal. The elements of the phaseadjustment circuit 182 operate similarly to the corresponding elementsof the phase adjustment circuit 142 discussed above in connection withFIGS. 3 and 4.

[0092] A current calculator 200 is coupled to the outputs of the currentdecoders 188 and the voltage-to-current transformer 198 to add the valueof the control current produced by the current decoders 188 to the valueof the base current, or to subtract the value of the control currentfrom the value of the base current. For example, the values produced bythe current decoders 188 corresponding to the counters A and B are addedto the value of the base current, whereas the values produced by thecurrent decoders 188 corresponding to the counters C and D aresubtracted from the value of the base current.

[0093] The current calculator 200 produces resulting current supplied toa control input of a CCO, such as a ring oscillator. When the EXT.CLKsignal is first applied, the CCO frequency is determined by the basecurrent. In response to the resulting current from the currentcalculator 200, the CCO frequency deviates so as to reduce phase andfrequency difference between the EXT.CLK and INT.CLK signals. The CCOoutput signal may be processed by a level shifting and buffering circuitto produce the INT.CLK signals.

[0094] When the PLL is out of lock, the frequency adjustment circuit 180operates in a mode of rough adjustment to bring the INT.CLK frequency atthe CCO output closer to the frequency of the external clock EXT.CLK. Asillustrated in FIG. 6, when the EXT.CLK frequency is higher than theINT.CLK frequency, the counter A counts the number of the EXT.CLKperiods in a highlevel half period of the INT.CLK signal. To determinethe number of the EXT.CLK periods in a low-level half period of theINT.CLK signal, the counter B may count the number of periods of theEXT.CLK/ signal in a high-level half period of the INT.CLK/ signal. Thecounters A and B may ignore the first period of the EXT.CLK and EXT.CLK/signals in a high-level half cycle of the INT.CLK and INT.CLK/ signals,and produce their counts only in response to the EXT.CLK and EXT.CLK/periods that follow the first period.

[0095] A high-level half cycle of the INT.CLK and INT.CLK/ signalsdefines an evaluation period of counting for the counters A and B,respectively. The evaluation period is followed by a transfer perioddefined by the next low-level half cycle of the INT.CLK and INT.CLKIsignals. During the evaluation period, the counters A and B producetheir output counts. During the transfer period, the produced counts areaccumulated by the corresponding adders 186.

[0096] Thus, when two or more EXT.CLK or EXT.CLK/ periods are detectedin a high-level half cycle of the INT.CLK or INT.CLK/ signal, thecounters A and B produce the corresponding counts represented by n-bitvalues. In the example illustrated in FIG. 6, each of the counters A andB detects two EXT.CLK periods. Accordingly, their counts are equal to 1,and may be represented by 0001. However, the counters C and D produce nocounts because the EXT.CLK frequency is higher than the INT.CLKfrequency.

[0097] The adders 186 coupled to the counters A and B accumulate then-bit counts produced during a predetermined number of INT.CLK orINT.CLK/ half cycles to generate the corresponding m-bit values. Thecurrent decoders 188 corresponding to the counters A and B produce thecontrol current having values representing the m-bit values produced bythe adders 186. These control current values are added to the value ofthe base current to increase the current supplied to the CCO. Inresponse, the CCO frequency increases to increase the INT.CLK frequencyso as to make the INT.CLK frequency closer to EXT.CLK frequency.

[0098] As illustrated in FIG. 7, when the EXT.CLK frequency is lowerthan the INT.CLK frequency, the counters A and B produce no counts.However, the counters C and D respectively count the number of INT.CLKperiods in high-level and low-level half cycles of the EXT.CLK signal.To obtain the required count, the counter D may count the number ofINT.CLK/ periods in a high-level half cycle of the EXT.CLK/ signal.

[0099] A high-level half cycle of the EXT.CLK and EXT.CLK/ signalsdefines an evaluation period of counting for the counters C and D,respectively. The evaluation period is followed by a transfer perioddefined by the next low-level half cycle of the EXT.CLK and EXT.CLK/signals. During the evaluation period, the counters C and D producetheir output counts. During the transfer period, the produced counts areaccumulated by the corresponding adders 186.

[0100] Thus, when two or more INT.CLK or INT.CLK/ periods are detectedin a high-level half cycle of the INT.CLK or INT.CLK/ signal, thecounters C and D produce the corresponding counts represented by n-bitvalues. In the example illustrated in FIG. 7, each of the counters C andD detects two INT.CLK periods. Accordingly, their counts are equal to 1,and may be represented by 0001.

[0101] The adders 186 coupled to the counters C and D accumulate then-bit counts produced during a predetermined number of EXT.CLK orEXT.CLK/ half cycles to generate the corresponding m-bit values. Thecurrent decoders 188 corresponding to the counters C and D produce thecontrol current having values representing the m-bit values produced bythe adders 186. These control current values are subtracted from thevalue of the base current to reduce the current supplied to the CCO. Inresponse, the CCO frequency decreases to reduce the INT.CLK frequency soas to make the INT.CLK frequency closer to EXT.CLK frequency.

[0102] Reference is now made to FIG. 8 illustrating another example ofthe PLL of the present application that includes a frequency adjustmentcircuit 202 comprising frequency dividers 204 and 206 arranged at itsinput. The frequency divider 206 is supplied with an external referenceclock EXT.CLK, whereas the frequency divider 204 is provided via afeedback loop with an internal clock INT.CLK produced at the output ofthe PLL. The dividers 204 and 206 are used for respectively dividing theINT.CLK frequency and the EXT.CLK frequency by a preset amount, forexample by 2.

[0103] The frequency divider 204 is coupled to one input of a counter208 having its another input supplied with the EXT.CLK signal. Thefrequency divider 206 is connected to one input of a counter 210,another input of which is provided with the INT.CLK signal. The counter208 may count the number of the EXT.CLK periods in a half cycle of thesignal produced by the divider 204. The counter 210 may count the numberof the INT.CLK periods in a half cycle of the signal produced by thedivider 206. The counters 208 and 210 produce n-bit counts representingthe results of their counting operations.

[0104] Adders 212 and 214 are respectively coupled to the outputs of thecounters 208 and 210 for accumulating the n-bit counts produced by thecorresponding counter to generate an m-bit value. Current decoders 216and 218 are respectively coupled to the outputs of the adders 212 and214 for producing the control current that represents the output valueof the corresponding adder.

[0105] A current generator 220 provides each of the current decoders 216and 218 with a reference value of current. The current decoders 216 and218 modify the reference current in accordance with the output values ofthe corresponding adders 212 and 214 to produce the control current.

[0106] A phase adjustment circuit 222 may comprise a phase detector 224supplied with the EXT.CLK signal and the INT.CLK signal to produce aphase error signal representing phase and frequency differences betweenthe EXT.CLK signal and the INT.CLK signal. The phase error signal isprocessed by a charge pump 226, a loop filter 228 and avoltage-to-current transformer 230 to produce a base currentcorresponding to the phase error signal. The elements of the phaseadjustment circuit 222 operate similarly to the corresponding elementsof the phase adjustment circuit 142 discussed above in connection withFIGS. 3 and 4.

[0107] A current calculator 232 is coupled to the outputs of the currentdecoders 216 and 218 and the voltage-to-current transformer 230 to addthe value of the control current produced by the current decoder 216 tothe value of the base current, or to subtract the value of the controlcurrent produced by the current decoder 218 from the value of the basecurrent.

[0108] The current calculator 232 produces resulting current supplied toa control input of a CCO, such as a ring oscillator. When the EXT.CLKsignal is first applied, the CCO frequency is determined by the basecurrent. In response to the resulting current from the currentcalculator 232, the CCO frequency deviates so as to reduce phase andfrequency difference between the EXT.CLK and INT.CLK signals. The CCOoutput signal may be processed by a level shifting and buffering circuitto produce the INT.CLK signals.

[0109] When the PLL is out of lock, the frequency adjustment circuit 202operates in a mode of rough adjustment to bring the INT.CLK frequency atthe CCO output closer to the frequency of the external clock EXT.CLK.

[0110] As illustrated in FIG. 9, when the EXT.CLK frequency is higherthan the INT.CLK frequency, the counter 208 operates, whereas thecounter 210 produces no counts.

[0111] In particular, the divider 204 divides the INT.CLK frequency, forexample, by 2 and supplies the counter 208 with the signal having thefrequency half as high as the INT.CLK frequency. Accordingly, a halfcycle of the output signal of the divider 204 is twice as long as a halfcycle of the INT.CLK signal. The counter 208 counts the number ofEXT.CLK periods in a half cycle of the output signal produced by thedivider 204. For example, the EXT.CLK periods may be counted in ahigh-level half cycle of the divided INT.CLK signal. The counter 208 mayignore the first period of the EXT.CLK signal in a highlevel half cycleof the divided INT.CLK signal, and produce its count only in response tothe EXT.CLK periods that follow the first period.

[0112] A high-level half cycle of the divided INT.CLK signal defines anevaluation period of counting. The evaluation period is followed by atransfer period defined by the next low-level half cycle of the dividedINT.CLK signal. During the evaluation period, the counter 208 producesits output count. During the transfer period, the produced count isaccumulated by the adder 212.

[0113] Thus, when two or more EXT.CLK periods are detected in ahigh-level half cycle of the divided INT.CLK signal, the counter 208produces the corresponding count represented by an n-bit value. In theexample, illustrated in FIG. 9, the counter 208 detects 4 periods of theEXT.CLK signal in a half cycle of the divided INT.CLK signal. Therefore,its count is equal to 3, and may be represented by 0011.

[0114] The adder 212 coupled to the counter 208 accumulates the n-bitcounts produced during a predetermined number of the half cycles togenerate the corresponding m-bit value. The current decoder 216 producesthe control current representing the m-bit value produced by the adder212. The control current value is added to the value of the base currentto increase the current supplied to the CCO. In response, the CCOfrequency increases to increase the INT.CLK frequency so as to make theINT.CLK frequency closer to EXT.CLK frequency.

[0115] As illustrated in FIG. 10, when the INT.CLK frequency is higherthan the EXT.CLK frequency, the counter 210 operates, whereas thecounter 208 produces no counts.

[0116] In particular, the divider 206 divides the EXT.CLK frequency, forexample, by 2 and supplies the counter 210 with the signal having thefrequency half as high as the EXT.CLK frequency. Accordingly, a halfcycle of the output signal of the divider 206 is twice as long as a halfcycle of the EXT.CLK signal. The counter 210 counts the number ofINT.CLK periods in a half cycle of the output signal produced by thedivider 206. For example, the INT.CLK periods may be counted in ahigh-level half cycle of the divided EXT.CLK signal. The counter 210 mayignore the first period of the INT.CLK signal in a high-level half cycleof the divided EXT.CLK signal, and produce its count only in response tothe INT.CLK periods that follow the first period.

[0117] A high-level half cycle of the divided EXT.CLK signal defines anevaluation period of counting. The evaluation period is followed by atransfer period defined by the next low-level half cycle of the dividedEXT.CLK signal. During the evaluation period, the counter 210 producesits output count. During the transfer period, the produced count isaccumulated by the adder 214.

[0118] Thus, when two or more INT.CLK periods are detected in ahigh-level half cycle of the divided EXT.CLK signal, the counter 210produces the corresponding count represented by an n-bit value. In theexample illustrated in FIG. 10, the counter 210 detects 4 periods of theINT.CLK signal in a half cycle of the divided EXT.CLK signal. Therefore,its count is equal to 3, and may be represented by 0011.

[0119] The adder 214 coupled to the counter 210 accumulates the n-bitcounts produced during a predetermined number of the half cycles togenerate the corresponding m-bit value. The current decoder 218 producesthe control current representing the m-bit value produced by the adder214. The control current value is subtracted from the value of the basecurrent to reduce the current supplied to the CCO. In response, the CCOfrequency decreases to reduce the INT.CLK frequency so as to make theINT.CLK frequency closer to EXT.CLK frequency.

[0120] The dividers 204 and 206 allow the evaluation period to beincreased. As a result, the accuracy of the frequency differencedetection is improved. As the divisor for the dividers 204 and 206 maybe variable, the operating parameters of the PLL may be adjustable.

[0121] Reference is now made to FIG. 11 schematically illustrating afurther embodiment of the PLL of the present invention having a fineadjustment circuit 240, in addition to a phase adjustment circuit 242and a frequency adjustment circuit 244, to carry out fine tuning of theCCO frequency when the internal clock frequency is close to the externalclock frequency. The fine adjustment circuit 240 includes a delaymonitor 246 supplied with an external reference clock EXT.CLK. Asdescribed in more detail later, the delay monitor 246 may comprise adelay line for delaying the EXI.CLK signal by delay time amountsslightly less and slightly more than a period of the CCO output signal.A signal supplied from the control input to the CCO may be used toadjust the delay time of the delay line. A comparator 248 is coupled tothe delay monitor 246 for comparing the input to the delay monitor 246with its outputs. The comparator 248 produces a value that representsfine tuning current to be added or subtracted from the control currentsupplied to the CCO input, in order to provide the fine tuning of theCCO. A current decoder 250 produces the fine tuning currentcorresponding to the value determined by the comparator 248. Thiscurrent is added to or subtracted from the control current supplied tothe CCO input depending on whether the EXT.CLK frequency is higher orlower than the CCO output frequency.

[0122] The phase adjustment circuit 242 comprises a phase detector 252,a charge pump 254, a loop filter 256, and a voltage-to-currenttransformer 258 that operate similarly to the corresponding elements ofthe phase adjustment circuit 142 described in connection with FIG. 4.The frequency adjustment circuit 244 comprises a frequency detector 260,an accumulator 262 and a current adjuster 264 that operate similarly tothe corresponding elements of the frequency adjustment circuit 148described in connection with FIG. 4.

[0123] A current calculator 266 is coupled to outputs of the currentdecoder 250, the voltage-to-current transformer 258 and the currentadjuster 264 for calculating the value of control current to be suppliedto a CCO 268. The output signal of the CCO 268 may be processed by thelevel shifting and buffering circuit 270 to produce an internal clocksignal INT.CLK at the CCO output frequency.

[0124] When the external reference clock EXT.CLK is first applied, thefrequency of the CCO 268 may be determined by base current produced bythe voltage-to-current transformer 258 in the phase adjustment circuit242. If the PLL is out of lock, the frequency adjustment circuit 244operates in a mode of rough frequency adjustment to bring the CCOfrequency closer to the frequency of the external clock EXT.CLK.

[0125] When the CCO frequency becomes closer to the EXT.CLK frequency,the PLL 140 may go to a fine frequency adjustment mode to performaccurate phase and frequency adjustment. In this mode, the fineadjustment circuit 240 provides the fine tuning of the CCO frequency tofurther reduce the frequency difference between the INT.CLK signal andthe EXT.CLK signal.

[0126] Reference is now made to FIG. 12 that shows an exemplaryembodiment of the PLL having a fine adjustment circuit 280, a phaseadjustment circuit 282 and a frequency adjustment circuit 284 to providethe fine tuning of the CCO frequency, in addition to frequency and phaseadjustments. The fine adjustment circuit 280 may comprise a frequencydivider 286 supplied with the external reference clock EXT.CLK. Forexample, the divider 286 may divide the EXT.CLK frequency by 2 toproduce a divided external clock signal DIV.EXT.CLK. A delay model 288is coupled to the output of the divider 286 to delay the DIV.EXT.CLKsignal. An inverter 287 may be provided to supply the inverted value ofthe DIV.EXT.CLK signal to one of the delay model inputs. As will bediscussed in more detail later, the delay model 288 has two outputs Aand B. The signal supplied from the output A may be delayed with respectto the DIV.EXT.CLK signal by a delay time slightly smaller than a periodof a CCO 340 provided to generate the internal clock signal INT.CLK. Thesignal supplied from the output B may be delayed with respect to theDIV.EXT.CLK signal by a delay time slightly larger than the period ofthe CCO.

[0127] A logic/latch circuit 290 is coupled to the outputs A and B ofthe delay model 288 to compare its input signal with the signalssupplied from the outputs A and B. The logic/latch circuit 290 producesan UP signal when rising edges of the signals supplied from the outputsA and B are delayed with respect to the rising edge of the DIV.EXT.CLKsignal by a time period larger than the period of the EXT.CLK signal,i.e. when the EXT.CLK frequency is higher than the INT.CLK frequency.The logic/latch circuit 290 generates a DOWN signal when rising edges ofthe the signals supplied from the outputs A and B are delayed withrespect to the rising edge of the DIV.EXT.CLK signal by a time periodsmaller than a period of the EXT.CLK signal, i.e. when the EXT.CLKfrequency is lower than the INT.CLK frequency.

[0128] The UP and DOWN signals are respectively supplied to adders 292and 294 which accumulate results of the comparison carried out by thelogic/latch circuit 290, and produce the corresponding m-bit values.Current decoders 296 and 298 supplied by a current generator 300 arerespectively connected to the outputs of the adders 292 and 294 toproduce control current representing the m-bit values produced by theadders 292 and 294. The current generator 300 provides each of thecurrent decoders 296 and 298 with a reference value of current. Thecurrent decoders 296 and 298 modify the reference current in accordancewith the output values of the corresponding adders 292 and 294 toproduce the control current.

[0129] The phase adjustment circuit 282 may comprise a phase detector302 supplied with the EXT.CLK signal and the INT.CLK signal to produce aphase error signal representing phase and frequency differences betweenthe EXT.CLK signal and the INT.CLK signal. The phase error signal issupplied to a charge pump 304, a loop filter 306 and avoltage-to-current transformer 308 to produce a base currentcorresponding to the phase error signal.

[0130] The frequency adjustment circuit 284 may comprise dividers 310and 312 arranged at its input. The divider 312 is supplied with theEXT.CLK signal, whereas the divider 314 is provided via a feedback loopwith the INT.CLK signal produced by the CCO at the output of the PLL.The dividers 310 and 312 are respectively connected to counters 314 and316 further supplied with the EXT.CLK and INT.CLK signals. The counters314 and 316 respectively count the number of the EXT.CLK and INT.CLKperiods in a half cycle of the signals produced by the dividers 310 and312. Adders 318 and 320 are respectively coupled to the counters 314 and316 for accumulating the n-bit counts produced by the correspondingcounter to generate an m-bit value. Current decoders 322 and 324supplied with a current generator 326 are respectively coupled to theoutputs of the adders 318 and 320 for producing the control current thatrepresents the m-bit value of the corresponding adders.

[0131] The elements of the phase adjustment circuit 282 and thefrequency adjustment circuit 284 may operate in a manner similar to theoperation of the corresponding elements of the phase adjustment circuit222 and the frequency adjustment circuit 202 illustrated in FIG. 8.

[0132] A current calculator 328 is coupled to the outputs of the currentdecoders 296 and 298 of the fine adjustment circuit 280, the currentdecoders 322 and 324 of the frequency adjustment circuit 284, and thevoltage-to-current transformer 308 of the phase adjustment circuit 282.When the EXT.CLK signal is first applied, the output current of thecurrent calculator 328 is determined by base current supplied from thevoltage-to-current transformer 308. For rough frequency adjustment, thecurrent calculator 328 adds the value of the control current produced bythe current decoder 322 to the value of the base current, or subtractsthe values of the control current produced by the current decoders 324from the value of the base current. For fine frequency adjustment, thecurrent calculator 328 adds the value of the control current produced bythe current decoder 296 to the value of the base current, or subtractsthe values of the control current produced by the current decoders 298from the value of the base current.

[0133] The output of the current calculator 328 is connected to thecontrol input of the CCO to control the phase and frequency of theINT.CLK signal produced by the CCO. Referring to FIG. 13, the CCO 340may be implemented by a ring oscillator composed of k inverter stages I,where k is an odd number. For example, the ring oscillator 340 may haveseven inverter stages I connected serially with each other. Theinverting and non-inverting outputs of the last inverter stage I arerespectively coupled to the inverting and non-inverting inputs of thefirst inverter stage I.

[0134] Referring to FIG. 14, the delay model 288 may be composed of morethan 2k serially connected inverter stages I to be capable of delaying aDIV.EXT.CLK signal produced at the output of the divider 286 by a delaytime larger than the period of the ring oscillator 340. For example, theoutput A may be provided at the output of inverter stage 2k-1, and theoutput B may be arranged at the output of inverter stage 2k+1. Thus,when the ring oscillator 340 contains seven inverter stages I, theoutput A may be provided at the output of the thirteen inverter stage I,whereas the output B may be arranged at the output of the fifteenthinverter stage I. The non-inverting input of the first inverter stage Iis fed with the DIV.EXT.CLK signal supplied from the divider 286. Theinverting input of the first inverter stage I receives the invertedvalue of the DIV.EXT.CLK signal supplied from the inverter 287.

[0135] As illustrated in FIG. 15, when the INT.CLK frequency at theoutput of the ring oscillator 340 is equal to the EXT.CLK frequency, therising edge of the signal supplied from the output A of the delay model288 is delayed with respect to the rising edge of the DIV.EXT.CLK by adelay time slightly smaller than the period of the INT.CLK signal at theoutput of the ring oscillator 340. The rising edge of the signalsupplied from the output B of the delay model 288 is delayed withrespect to the rising edge of the DIV.EXT.CLK by a delay time slightlylarger than the period of the INT.CLK signal. As a result, no UP signalor DOWN signal is generated at the output of the logic/latch circuit290. For example, the logic/latch circuit 290 may detect logic levels ofthe output A and output B signals at the instant in which theDIV.EXT.CLK signal makes the transition from its high level to its lowlevel. If the logic levels of the output A and output B signals aredifferent, the logic/latch circuit 290 produces no UP and DOWN signals.

[0136] Referring to FIG. 16, when the INT.CLK frequency at the output ofthe ring oscillator 340 is higher than the INT.CLK frequency, the risingedges of the output A and output B signals are delayed with respect tothe rising edge DIV.EXT.CLK by a delay time smaller than the period ofthe EXT.CLK signal. The logic/latch circuit 290 may detect that both theoutput A and output B signals are at a high level H at the instant inwhich the DIV.EXT.CLK signal goes low. As a result, the DOWN signal maybe supplied to the adder 294.

[0137] The DOWN signal may be accumulated in the adder 294 for apredetermined time period to produce an m-bit DOWN value supplied to thecurrent decoder 298. In response, the current decoder 298 produces avalue of control current corresponding to the DOWN value. The currentcalculator 328 subtracts the produced control current from the basecurrent supplied from the phase adjustment circuit 282. Accordingly, theresulting current supplied to the input of the ring oscillator 340decreases. As a result, the INT.CLK frequency at the output of the ringoscillator 340 reduces so as to be closer to the EXT.CLK frequency. TheCCO output signal may be processed by a level shifting and bufferingcircuit to produce the INT.CLK signal. The fine adjustment procedurecontinues until the logic/latch circuit 290 detects that the output Asignal is at a high level and the output B signal is at a low level atthe instant in which the DIV.EXT.CLK signal makes its transition from ahigh level to a low level.

[0138] As illustrated in FIG. 17, when the INT.CLK frequency at theoutput of the ring oscillator 340 is lower than the INT.CLK frequency,the rising edges of the output A and output B signals are delayed withrespect to the rising edge of the DIV.EXT.CLK by a delay time largerthan the period of the EXT.CLK signal. The logic/latch circuit 290 maydetect that both the output A and output B signals are at a low level Lat the instant in which the DIV.EXT.CLK signal goes low. When logiclevels at the outputs A and B are at a low level, the logic/latchcircuit 290 may produce an UP signal supplied to the adder 292.

[0139] The UP signal is accumulated in the adder 292 for a predeterminedtime period to produce an m-bit UP value supplied to the current decoder296. In response, the current decoder 298 produces a value of controlcurrent corresponding to the UP value. The current calculator 328 addsthe produced control current to the base current supplied from the phaseadjustment circuit 282. Accordingly, the resulting current supplied tothe input of the ring oscillator 340 increases. As a result, the INT.CLKfrequency at the output of the ring oscillator 340 increases so as to becloser to the EXT.CLK frequency. The CCO output signal may be processedby a level shifting and buffering circuit to produce the INT.CLK signal.The fine frequency adjustment continues until the logic/latch circuit290 detects that the output A signal is at a high level and the output Bsignal is at a low level at the instant in which the DIV.EXT.CLK signalmakes its transition from a high level to a low level.

[0140] As the time interval between the rising edges of the output A andoutput B signals is very small, the fine adjustment circuit 280 providesvery accurate phase and frequency adjustment of the INT.CLK signal withrespect to the EXT.CLK signal.

[0141] The resulting current from the output of the current calculator328 may be fed back to the delay model 288 to adjust its delay time inaccordance with the value of the current at the input of the CCO 340,i.e. in accordance with the CCO output frequency variations. Forexample, when the current at the CCO input increases to increase theINT.CLK frequency at the output of the ring oscillator 340, the periodof the CCO output reduces. Accordingly, the delay time of the delaymodel 288 is reduced to match the reduction of the CCO period.

[0142] By contrast, when the current at the CCO input decreases toreduce the INT.CLK frequency at the CCO output, the CCO periodincreases. To match this increase, the delay model 288 is adjusted toincrease its delay time.

[0143] When the PLL is out of lock, it operates in a rough frequencyadjustment mode, in which the frequency adjustment circuit 284 dominatesover the phase adjustment circuit 282 and the fine adjustment circuit280. When the frequency adjustment circuit 284 brings the INT.CLKfrequency closer to the frequency of the external clock EXT.CLK, the PLLcarries out a fine adjustment mode, in which the fine adjustment circuit280 interacts with the phase adjustment circuit 282 to more accuratelyadjust the INT.CLK frequency with respect to the EXT.CLK frequency.

[0144] As discussed above in connection with FIG. 2 that illustrates anexemplary system in which the PLL of the present invention may beemployed, the command decoder 126 decodes the external commands togenerate command clocks A-E for controlling various elements of the PLLin the internal synchronous signal generator 104 to produce the INT.CLKsignal. FIG. 18 illustrates supplying the command clocks A-E to elementsof the PLL having the phase adjustment circuit 222 and the frequencyadjustment circuit 202 shown in FIG. 8. In particular, clock A may besupplied to the current generator 220 in the frequency adjustmentcircuit 202. Clock B may be supplied to the current calculator 232 thatprovides a CCO 350 with a resulting control current. Clock C may besupplied to a level shifting and buffering circuit 352 coupled to theoutput of the CCO 350. Clock D may be sent to the phase detector 224 inthe phase adjustment circuit 222, and to a clock buffer 356 that may beused for buffering the internal clock signal INT.CLK before supplying itto the phase detector 224. Finally, clock E may be supplied to a clockbuffer 354 that may be connected to the output of the level shifting andbuffering circuit 352 to provide buffering of its output signal. Theoutput clock signal produced by the clock buffer 354 is supplied tocircuitry external with respect to the internal synchronous signalgenerator 104.

[0145] When the PLL is in a power off mode, the current generator 220 isdisabled by clock A. As a result, no current is supplied by thisgenerator. The current generator 220 is activated when power is suppliedto the PLL. After a stand-by time period, clock B is supplied to enablethe current calculator 232 to provide the CCO 350 with control current.Clock C enables the level shifting and buffering circuit 352 to outputthe signal produced by the CCO 350. Thereafter, clock D is supplied toinitiate a locking procedure for bringing the PLL into lock. This clockenables the clock buffer 356 to supply the phase detector with theINT.CLK signal. Also, clock D enables the clock buffer 102 to providethe PLL with the EXT.CLK signal. Clock E supplied after the PLL isbrought into lock, enables the clock buffer 354 to deliver the producedinternal clock INT.CLK to the external circuitry.

[0146] After the PLL is brought into lock, a self-refreshing mode may becarried out when the external clock EXT.CLK is not provided. Afreerunning clock may be supplied from an additional ring oscillator tocontrol the PLL operations in this mode. The free-running clock suppliedinstead of the EXT.CLK signal allows the PLL to quickly return to alocked condition.

[0147] Hereinafter, the state transition of the PLL in FIG. 18 (theinternal synchronous signal generator 104 shown in FIG. 2) will bedescribed with reference to FIG. 19. Here, FIG. 19 illustrates anexample of the state transition of the PLL when it is used as theinternal synchronous signal generator 104 of the clock synchronous typesemiconductor memory device shown in FIG. 2.

[0148] When PLL is in a power off state (state S1) with no power beingsupplied, command clocks A-E output from command decoder 126 shown inFIG. 2 are all in an inactive state.

[0149] When power is supplied and the voltage level of power supplyvoltage Vcc increases, PLL initially enters a power up state (1) (stateS2). In this state, command clock A is driven to an active state, whileall the other command clocks B-E are held at an inactive state. As aresult, only the current generator 220 in FIG. 18 is enabled to generatea current. This power up state (1) is a state in which power is simplysupplied and thus the voltage level of power supply voltage Vcc isincreased, in which the operations of the internal circuits are haltedby an internally generated power on reset signal POR.

[0150] When power supply voltage Vcc becomes stable, power on resetsignal POR is activated to allow PLL to shift from the state S2 to apower up state (2) (state S3). In this power up state (2), commandclocks A, B are rendered active, while the other command clocks C-Eremain inactive. As a result, current calculator 232 in FIG. 18 isenabled to provide a control current to CCO 350. As command clock D isin an inactive state, PLL is in a free-running, oscillating state,performing no locking operation.

[0151] When clock enable signal CKE is set to an active state (an onstate), PLL shifts from the state S3 to a chip select state (1) (stateS4) allowing accessing to this semiconductor memory device. With thisclock enable signal CKE in an active state, the semiconductor memorydevice in FIG. 2 enters a state allowing acceptance of an externallysupplied signal. In this chip select state (1), command clocks A-C arein an active state, while command clocks B, E remain inactive.Therefore, PLL does not perform the locking operation yet in this statebecause it has just been driven to the chip select state, and a stableclock signal synchronized with the externally supplied clock signalEXT.CLK is not generated yet.

[0152] In a predetermined time period after entry into the chip selectstate (1), PLL transits from the state S4 to a chip select state(2)(state S5), in which command clocks A-D are driven to an activestate. Command clock E remains inactive, thereby keeping clock buffer354 in FIG. 18 in a disabled state. As command clock B is activated, PLLin FIG. 18 initiates the locking operation according to externallysupplied clock signal EXT.CLK and internal clock signal supplied fromlevel shifting and buffering circuit 352, to drive the internal clocksignal INT.CLK into a locked state to the external clock signal EXT.CLK.

[0153] In the chip select state (2) (state S5), a row select operationis performed in the semiconductor memory device when an active commandACT is provided. With this active command ACT provided, the row selectoperation should be performed within the semiconductor memory device, sothat command clock E is activated to provide internal clock signalINT.CLK supplied from clock buffer 354 in FIG. 18 to each of theinternal circuits. In this array active state (state S6), a word line iskept at a selected state. When the precharge command PRG is provided,PLL returns from the array active state (state S6) back to the chipselect state (2).

[0154] When a self refresh command SREF is provided in the array activestate (state S6), the semiconductor memory device enters a self refreshstate (state S7), in which a memory cell data is refreshed with arefresh address generated using an internal refresh address counter. Theself refresh operation is performed using a refreshing oscillator and arefresh counter for counting the number of clocks of the refreshingoscillator which are internally provided for refreshing. In this selfrefresh state (state S7), the refreshing oscillator is set to an activestate (an on state) to allow a control signal for instructing the rowselect operation to be generated at a predetermined interval (byinternal control signal generator 106 shown in FIG. 2). Since theinternal clock signal from PLL shown in FIG. 18 is unnecessary for theinternal circuit operations in this state, command clocks A-E are alldriven to an inactive state. In this state, different from the power offstate, command clocks A-E are only driven inactive, while the m-bitbinary value to be applied to current decoders 216, 218 in FIG. 18 ismaintained. Keeping all the command clocks A-E inactive in this selfrefresh state (state S7) allows reduction in current consumption.

[0155] When the self refresh state (state S7) is complete, a selfrefresh end command ESREF is provided. Since PLL is required to performthe locking operation to reset the self refresh state, command clocksA-D are driven to an active state. Meanwhile, command clock E remainsinactive. In the shift from the self refresh state (state S7) to thechip select state (2) (state S5), the array temporarily enters aprecharge state. As the (binary) current value for generating aninternal clock signal in PLL is maintained, the use of this value(representing a phase and frequency in its locked state) substantiallyreduces the recovery time required for the PLL to reinstate a lockedstate.

[0156] PLL goes from the array active state to a power down mode forreducing current consumption, for which power down mode two states arepossible: a power down state (1) (state S8); and a clock down state(state S9). In the power down state (1) (state S8), the external clocksignal EXT.CLK is continuously supplied with generation of the internalclock signal INT.CLK stopped within the semiconductor memory device,thereby keeping the device in this power down mode. In the clock downstate (state S9), the frequency of the externally supplied clock signalEXT.CLK is divided by a factor of N to decrease the current consumptionin external devices as well as in the clock buffer. Since external clocksignal EXT.CLK is continuously provided in the power down state (1)(state S8), only the command clock E is made inactive, while the othercommand clocks A-D are held at an active state to keep PLL in the lockedstate. In this manner, when no access is attempted to the semiconductormemory device or no operation is performed in a system using this devicefor a relatively short time period, PLL is temporarily driven to thepower down state (1) for reducing current consumption, and then drivenback to the previous array active state (state S6). Here, since theexternal clock signal EXT.CLK and the internal clock signal INT.CLK areboth in a locked state, PLL can return to the array active state (stateS6) quickly to perform the next operation.

[0157] In the clock down state (state S9), a clock signal divided infrequency by a factor of N is externally supplied. Similarly in thisstate, only command clock E is made inactive, while the other commandclocks A-D remain active. Although not shown in FIG. 18, an Nfrequency-divider is inserted between level shifting and bufferingcircuit 352 and clock buffer 356 or between clock buffer 356 and phasedetector 224 in the clock down state (state S10). The clock output fromthis internal frequency-divider and the externally supplied,frequency-divided clock signal are compared to allow the lockingoperation to be continued. Using this frequency-divided clock signal,the operation frequencies of the comparator and the buffer are reducedby a factor of N, and thus current consumption is further reduced. PLLis shifted to this clock down state S9 by a clock down command CKDWNwhen no access is made to the semiconductor memory device for arelatively long time. Meanwhile, the shift to the power down state (1)(state S8) is effected by a power down command PWD1.

[0158] The semiconductor memory device in the chip select state (2) canmake a transition to a power down state. This shift from the chip selectstate (2) (state S5) to the power down state (2) (state S10) occurs whena power down command PWD2 is provided. The power down state (2)corresponds to a state in which the semiconductor memory device is notin use for a relatively long time (e.g. in which a portable terminalonly needs to retain data). Generation of external clock signal EXT.CLKis terminated, and in response, the lock is released. As a result,command clocks A-E are all driven to an inactive state, whereby almostno current is consumed in this semiconductor memory device.

[0159] Except for the power up state, driving of respective commandclocks A-E to active/inactive states according to the PLL states areimplemented by the command decoder 126 shown in FIG. 2 in response to anexternally supplied command. Upon power-up, command decoder 126 performssequential activation of command clocks A, B according to the power onreset signal POR supplied from a power on reset circuit, not shown.Here, any structure may be used as long as it is capable of drivingcommand clock A to an active state, then activating the power on resetsignal POR and then driving command clock B to an active state uponpower-up.

[0160] In the PLL shown in FIG. 18, a frequency-divider is used in theclock down state to perform the locking operations between thefrequency-divided internal clock signal and the externally supplieddivided clock signal. This is implemented by connecting thefrequency-divider between level shifting and buffering circuit 352 andclock buffer 356 or between phase detector 224 and clock buffer 356 by aselector circuit and the frequency-divider is activated, when the clockdown command CKDWN is provided to designate the clock down state (stateS9). Here, the structure to be used has only to select either thefrequency-divided internal clock signal of this frequencydivider or theinternal clock signal from level shifting and buffering circuit 352,depending on whether PLL is in the clock down state (state S9) or not.

[0161] It is to be understood that, although the description was madeabout PLL (see FIG. 18) in the above, the state transition as shown inFIG. 19 can be applied to another synchronous circuit employing, forexample, a Delayed Locked Loop (DLL).

[0162] There accordingly has been described a PLL that employs separatephase a frequency adjustment circuits to adjust the frequency of aproduced internal clock independently from adjusting its phase. Thephase adjustment circuit determines a phase error between the internalclock and an external clock, and averages the phase error over apredetermined time period to produce the corresponding control current.The frequency adjustment circuit detects the difference between thefrequency of the internal clock and the frequency of the external clockto determine a frequency error. An accumulator accumulates the frequencyerror during the predetermined time period to produce the correspondingcontrol current. Based on values of the control currents produced by thephase and frequency adjustment circuits, a current calculator calculatesa resulting value of the control current to be applied to a CCO tomodify its frequency so as reduce the frequency and phase differences.

[0163] In this disclosure, there are shown and described only thepreferred embodiments of the invention, but it is to be understood thatthe invention is capable of changes and modifications within the scopeof the inventive concept as expressed herein.

What is claimed is:
 1. A system for generating an internal clock signalin response to an external clock signal, comprising: a phase adjustmentcircuit responsive to said external clock signal and said internal clocksignal for producing a phase adjustment signal representing differencebetween phase of said external clock signal and phase of said internalclock signal, a frequency adjustment circuit responsive to said externalclock signal and said internal clock signal for producing a frequencyadjustment signal representing difference between frequency of saidexternal clock signal and frequency of said internal clock signal, acontrol value calculator responsive to said phase adjustment signal andsaid frequency adjustment signal for producing a resulting controlsignal, and a signal-controlled oscillator responsive to said resultingcontrol signal for producing said internal clock signal at an internalclock frequency deviating in response to said resulting control signal.2. The system of claim 1, wherein said frequency adjustment circuitcomprises a frequency detector responsive to said external clock signaland said internal clock signal for producing an instantaneous value of afrequency error signal indicating difference between instantaneousfrequencies of the internal clock signal and the external clock signal.3. The system of claim 2, wherein said frequency adjustment circuitfurther comprises an accumulator coupled to said frequency detector foraccumulating instantaneous values of the frequency error signal over apreset time period to produce an accumulated signal indicating anaverage value of the frequency difference for the preset time period. 4.The system of claim 3, wherein said frequency adjustment circuit furthercomprises an adjusting circuit coupled to said accumulator for adjustingsaid accumulated signal to produce said frequency adjustment signal. 5.The system of claim 1, wherein said frequency adjustment circuitcomprises a first counter responsive to said external clock signal andsaid internal clock signal for counting the number of periods of theexternal clock signal in a half cycle of the internal clock signal inwhich the internal clock signal is at a first logic level.
 6. The systemof claim 5, wherein said frequency adjustment circuit further comprisesa second counter responsive to said external clock signal and saidinternal clock signal for counting the number of periods of the externalclock signal in a half cycle of the internal clock signal in which theinternal clock signal is at a second logic level.
 7. The system of claim6, wherein said frequency adjustment circuit further comprises a thirdcounter responsive to said external clock signal and said internal clocksignal for counting the number of periods of the internal clock signalin a half cycle of the external clock signal in which the external clocksignal is at the first logic level.
 8. The system of claim 7, whereinsaid frequency adjustment circuit further comprises a fourth counterresponsive to said external clock signal and said internal clock signalfor counting the number of periods of the internal clock signal in ahalf cycle of the external clock signal in which the external clocksignal is at the second logic level.
 9. The system of claim 8, whereinsaid frequency adjustment circuit further comprises first, second, thirdand fourth adders respectively coupled to said first, second, third andfourth counters for accumulating n-bit counts produced by said first,second, third and fourth counters to generate m-bit accumulated values.10. The system of claim 9, wherein said frequency adjustment circuitfurther comprises first, second, third and fourth decoders respectivelycoupled to said first, second, third and fourth adders to generatefirst, second, third and fourth frequency control values supplied tosaid control value calculator.
 11. The system of claim 10, wherein saidcontrol value calculator is responsive to said first, second, third andfourth frequency control values, and a base value representing saidphase adjustment signal, for adding said first and second frequencycontrol values to said base value, and for subtracting said third andfourth frequency control values from said base value.
 12. The system ofclaim 11, wherein said frequency adjustment circuit further comprises areference current generator for supplying said first, second, third andfourth decoders with reference current to present said first, second,third and fourth frequency control values as first, second, third andfourth frequency control currents.
 13. The system of claim 12, whereinsaid base value is represented by base current.
 14. The system of claim13, wherein said control value calculator is responsive to said first,second, third and fourth frequency control currents and said basecurrent for producing resulting control current supplied to saidsignal-control oscillator to adjust frequency and phase of said internalclock signal in accordance with a value of said resulting controlcurrent.
 15. The system of claim 1, wherein said frequency adjustmentcircuit comprises a first frequency divider supplied with said internalclock signal for producing a divided internal clock signal at afrequency equal to the frequency of the internal clock signal divided bya preset number.
 16. The system of claim 15, wherein said frequencyadjustment circuit further comprises a second frequency divider suppliedwith said external clock signal for producing a divided external clocksignal at a frequency equal to the frequency of the external clocksignal divided by the preset number.
 17. The system of claim 16, whereinsaid frequency adjustment circuit further comprises a first clockcounter coupled to said first frequency divider and supplied with saidexternal clock signal for counting the number of periods of the externalclock signal in a half cycle of the divided internal clock signal. 18.The system of claim 17, wherein said frequency adjustment circuitfurther comprises a second counter coupled to said second frequencydivider and supplied with said internal clock signal for counting thenumber of periods of the internal clock signal in a half cycle of thedivided external clock signal.
 19. The system of claim 18, wherein saidfrequency adjustment circuit further comprises first and second addersrespectively coupled to said first and second counters for accumulatingn-bit counts produced by said first and second counters to generatem-bit accumulated values.
 20. The system of claim 19, wherein saidfrequency adjustment circuit further comprises first and second decodersrespectively coupled to said first and second adders to generate firstand second frequency control values supplied to said control valuecalculator.
 21. The system of claim 20, wherein said control valuecalculator is responsive to said first and second frequency controlvalues, and a base value represented by said phase adjustment signal foradding said first frequency control value to said base value, and forsubtracting said second frequency control value from said base value.22. The system of claim 1, further comprising a fine adjustment circuitsupplied with said external clock signal for providing fine frequencytuning of said signal-controlled oscillator, in addition to roughfrequency adjustment provided by said frequency adjustment circuit, andphase adjustment provided by said phase adjustment circuit.
 23. Thesystem of claim 22, wherein said fine adjustment circuit comprises adelay monitor for delaying said external clock signal by a delay amountdefined by a period of the signal-controlled oscillator.
 24. The systemof claim 23, wherein said fine adjustment circuit further comprises acomparator for comparing a delayed external clock signal produced bysaid delay monitor with said external clock signal to generate a finecontrol signal.
 25. The system of claim 24, wherein said control valuecalculator is responsive to said fine control signal for modifying saidresulting control signal.
 26. The system of claim 22, wherein said fineadjustment circuit comprises a delay model responsive to said externalclock signal for producing a first output signal delayed by a firstdelay time smaller than a period of said signal-controlled oscillator,and for producing a second output signal delayed by a second delay timelarger than the period of said signal-controlled oscillator.
 27. Thesystem of claim 26, wherein said fine adjustment circuit furthercomprises a logic circuit coupled to said delay model and supplied withan input signal to said delay model for determining logic levels of saidfirst and second output signals when said input signal goes from a firstlevel to a second level.
 28. The system of claim 27, wherein said logiccircuit is arranged to produce a down signal when both said first andsecond output signals are at the first level when said input signal goesfrom the first level to the second level.
 29. The system of claim 28,wherein said logic circuit is arranged to produce an up signal when bothsaid first and second output signals are at the second level when saidinput signal goes from the first level to the second level.
 30. Thesystem of claim 29, wherein said control value calculator is responsiveto said logic circuit for increasing a value of said resulting controlsignal in response to said up signal, and for decreasing the value ofsaid resulting control signal in response to said down signal.
 31. Thesystem of claim 30, wherein said fine adjustment circuit furthercomprises a frequency divider coupled to said delay model for producingsaid input signal at a frequency equal to frequency of said externalclock signal divided by a predetermined amount.
 32. The system of claim30, wherein said fine adjustment circuit further comprises a first addercoupled to said logic circuit for accumulating instantaneous values ofthe up signal to generate m-bit accumulated values of the up signal. 33.The system of claim 32, wherein said fine adjustment circuit furthercomprises a second adder coupled to said logic circuit for accumulatinginstantaneous values of the down signal to generate m-bit accumulatedvalues of the down signal.
 34. The system of claim 33, wherein saidfrequency adjustment circuit further comprises first and second decodersrespectively coupled to said first and second adders to generate firstand second fine tuning values supplied to said control value calculator.35. The system of claim 34, wherein said control value calculator isresponsive to said first and second fine tuning values, and a base valuerepresenting said phase adjustment signal for adding said first finetuning value to said base value, and for subtracting said second finetuning values from said base value.
 36. The system of claim 35, whereinsaid control value calculator is further responsive to a frequencycontrol value produced by said frequency adjustment circuit formodifying said resulting control signal in accordance with saidfrequency control value.
 37. The system of claim 36, wherein saidsignal-controlled oscillator comprises a ring oscillator having kserially connected inverter stages.
 38. The system of claim 37, whereinsaid delay model comprises more than 2k serially connected delay stagessimilar to the inverter stages of said ring oscillator.
 39. The systemof claim 38, wherein said delay model is arranged to produce said firstoutput signal at an output of delay stage 2k-l, where l is an integer.40. The system of claim 39, wherein said delay model is arranged toproduce said second output signal at an output of delay stage 2k+l. 41.The system of claim 40, wherein said fine adjustment circuit furthercomprises a reference current generator for supplying said first andsecond decoders with reference current to present said first and secondfine tuning values as first and second fine tuning currents.
 42. Thesystem of claim 41, wherein said base value is represented by basecurrent, and a frequency control value is represented by frequencycontrol current.
 43. The system of claim 42, wherein said control valuecalculator is responsive to said first and second fine tuning currents,said frequency control current and said base current for producingresulting control current supplied to said ring oscillator to tunefrequency of said ring oscillator in accordance with said resultingcontrol current.
 44. A method of producing an internal clock signal insynchronism with an external clock signal, comprising the steps of:comparing phase of said internal clock signal with phase of saidexternal clock signal to produce a phase adjustment signal representingdifferences in phase and frequency between said internal clock signaland said external clock signal, comparing frequency of said internalclock signal with frequency of said external clock signal independentlyfrom said step of phase comparing, to produce a frequency adjustmentsignal representing difference between the frequency of said internalclock signal and the frequency of said external clock signal, producinga control signal representing said phase adjustment signal and saidfrequency adjustment signal, and controlling a signal-controlledoscillator by said control signal to produce said internal controlsignal synchronized with said external control signal.
 45. The method ofclaim 44, wherein said steps of phase comparing and frequency comparingare carried out by separate circuits.
 46. The method of claim 45,further comprising the step of fine tuning said signal-controlledoscillator when the frequency of said internal clock signal is close tothe frequency of said external clock signal.
 47. The method of claim 46,wherein said step of fine tuning comprising the step of delaying theexternal clock signal by a delay time defined by a period of saidsignal-controlled oscillator.
 48. The method of claim 47, wherein saidstep of fine tuning further comprises the step of comparing a delayedexternal clock signal with the external clock signal to produce a finetuning signal.
 49. The method of claim 48, wherein said control signalis produced so as to represent said phase adjustment signal, saidfrequency adjustment signal and said fine tuning signal.
 50. A memorydevice supplied with an external clock signal, comprising: a memory cellarray for storing data, and an internal synchronous clock signalgenerator responsive to said external clock signal for producing aninternal clock signal supplied to internal circuits of said memorydevice to control various data reading and writing operations, saidinternal synchronous clock signal generator including: a phaseadjustment circuit responsive to said external clock signal and saidinternal clock signal for producing a phase adjustment signalrepresenting difference between phase of said external clock signal andphase of said internal clock signal, a frequency adjustment circuitresponsive to said external clock signal and said internal clock signalfor producing a frequency adjustment signal representing differencebetween frequency of said external clock signal and frequency of saidinternal clock signal, a control value calculator responsive to saidphase adjustment signal and said frequency adjustment signal forproducing a resulting control signal, and a signal-controlled oscillatorresponsive to said resulting control signal for supplying said internalcircuits with said internal clock signal modified in response to saidresulting control signal.